PLL Components for Low Power Applications

In communication and other electronics applications, frequency synthesizer plays an important role by generating carrier frequencies and clock signal. We always desire a stable and noise free output frequency in communication systems. Phase Locked Loop (PLL) is the best option in the entire available frequency synthesizer due the feedback system. VCO itself generates a frequency but due to open loop system its stability is less as compared to Phase Locked Loop (PLL).

Power consumption is an important factor for the electronics circuits that students learn in top private engineering colleges in UP, because consumed power is dissipated in the form of heat which affects the working of the electronics circuit and most of devices are chargeable, where battery life is directly dependent on the power consumption. We use communication devices in bio-transplantable devices also where we can provide power easily. So low power consumption is highly desirable.

Power consumption is directly proportional to the square of the supply voltage. If supply voltage is less then power consumption is less. But with the low supply voltage there are several challenges e.g. low voltage headroom etc.

For fulfilling these requirements a circuit Phase locked loop is good option. Phase locked loop output is much pure spectral than the normal oscillator. In normal oscillator there are 20 % frequency drift, which can create a big problem in the operation of these circuits. In current time we are totally dependent on PLL for frequency generation and phase tracking.

In all semiconductor devices power consumption is a critical factor, because most of the hand held devices are chargeable where battery lifetime is directly dependent on the consumed power. In these devices PLLs are regarded as one of the most power consuming components.

So if we will reduce the power consumption in the PLLs then most of the devices could be highly efficient as it is studied in Electronics Engineering in Greater Noida.

If we take a example of biomedical transplantable devices. In that devices power consumption is the biggest factor because in we could not supply power externally. Because several wireless standard operates at frequency range from 900-5200 MHz and in 2009 Federal Communications Commission (FCC) announced a bio-medical device for the diagnose purpose and they allotted 5MHz bandwidth between the range 401-406 MHz for medical purpose. So It can be said that optimizing the PLL in aforementioned frequency range is necessity now.

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